In this document, I will give a high level overview of RISC and CISC system, outlining the pro's and con's of each system and give example of where each of them might be used
CISC standas for Complex Instruction Set Computer. A CISC based computer has a rich instruction set allowing you to encode very complex operations into a single instruction. This leads to a larger number of instructions available for the compiler to use when the system is executing an application.
An example of a CISC instruction in the x86 Instruction Set Architecture (ISA) is:
REP MOVSB
The REP prefix tells the processor to repeat the following instruction a number of times based on the value of the CX register. The MOVSB instruction them moves a byte from the source location SI to the destination location DI, whilst incrementing both SI and DI after each iteration.
Reduced Instruction Set Computer (RISC) is a computer based on a processor architecture that has a minimal set of instructions. For example, loading and storing to memory along with arithmetic and logical operations and branching.
An example of a RISC instruction in the Arm ISA is:
MOV r1 r2
This will move the contents of r2 into r1.
A CISC based architecture can use less application memory to encode its functionality. This is because one CISC instruction can represent many RISC based instructions. The downside of this is that a CISC instruction can take more that one clock cycle to complete.
A RISC based process on the other hand is far simpler, only containing the bare minimum operations to enable the compiled code to operate correctly. This simple architecture is able to guarantee one instruction execution per clock cycle which can help when designing a real time operating system where you need a response within a guaranteed timeframe.
The physical implementation of a CISC system tends to be bigger, requiring larger chips to implement the bigger instruction decode block. Due to this increased size, CISC processors tend to be more expensive as silicon area correlates with cost. Conversely, RISC based processors tend to use less power to operate as they have a much simpler decode block in the systems Fetch-Decode-Execute cycle.
Each architecture has is unique characteristics which suits different use-cases. There is not one that is better than the other. But if I were building a highly embedded system that had to comsume milliwats of power to complete its function wilst being powered by a battery, I think I would be choosing a RISC base computer architecture.